View M2S56D20TP-75_3217444.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 1 m2s56d20tp is a 4-bank x 16777216-word x 4-bit, m2s56d30tp is a 4-bank x 8388608-word x 8-bit, double data rate synchronous dram, with sstl_2 interface. all control and address signals are referenced to the rising edge of clk. input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of clk. the m2s56d20/30 tp achieves very high speed data rate up to 133mhz, and are suitable for main memory in computer systems. - vdd=vddq=2.5v?.2v - double data rate architecture; two data transfers per clock cycle - bidirectional, data strobe (dqs) is transmitted/received with data - differential clock inputs (clk and /clk) - dll aligns dq and dqs transitions with clk transitions edges of dqs - commands entered on each positive clk edge; - data and data mask referenced to both edges of dqs - 4 bank operation controlled by ba0, ba1 (bank address) - /cas latency- 1.5/2.0/2.5 (programmable) - burst length- 2/4/8 (programmable) - burst type- sequential / interleave (programmable) - auto precharge / all bank precharge controlled by a10 - 8192 refresh cycles /64ms (4 banks concurrent refresh) - auto refresh and self refresh - row address a0-12 / column address a0-9,11(x4)/ a0-9(x8) - sstl_2 interface - 400-mil, 66-pin thin small outline package (tsop ii) - fet switch control(/qfc) - jedec standard preliminary some of contents are subject to change without notice. description features 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nu/qfc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss 66pin tsop(ii) 400mil width x 875mil length 0.65mm lead pitch row a0-12 column a0-9,11(x4) a0-9 (x8) x8 pin configuration (top view)
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 2 clk,/clk : master clock cke : clock enable /cs : chip select /ras : row address strobe /cas : column address strobe /we : write enable dq0-7 : data i/o dqs : data strobe dm : write mask /qfc : fet switch control vref : reference voltage pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd nu,/qfc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss 66pin tsop(ii) 400mil width x 875mil length 0.65mm lead pitch row a0-12 column a0-9,11(x4) a0-9 (x8) vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd nu,/qfc nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm /clk clk cke nc a12 a11 a9 a8 a7 a6 a5 a4 vss x8 x4 a0-12 : address input ba0,1 : bank address input vdd : power supply vddq : power supply for output vss : ground vssq : ground for output
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 3 type designation code this rule is applied to only synchronous dram family. mitsubishi main designation speed grade 10: 125mhz@cl=2.5,100mhz@cl=2.0 75: 133mhz@cl=2.5,100mhz@cl=2.0 package type tp: tsop(ii) process generation function reserved for future use organization 2 n 2: x4, 3: x8 ddr synchronous dram density 56: 256m bits interface v:lvttl, s:sstl_3, _2 memory style (dram) m 2 s 56 d 3 0 tp - block diagram /cs /ras /cas /we dm memory array bank #0 dq0 - 7 i/o buffer memory array bank #1 memory array bank #2 memory array bank #3 mode register control circuitry address buffer a0-12 ba0,1 clock buffer clk,/clk cke control signal buffer /qfc qfc&qs buffer dqs dll
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 4 pin function clk,/clk input clock: clk and /clk are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of clk and negative edge of /clk. output (read) data is referenced to the crossings of clk and /clk (both directions of crossing). cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke becomes asynchronous input. self refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-12 input a0-12 specify the row / column address in conjunction with ba0,1. the row address is specified by a0-12. the column address is specified by a0-9,11(x4) and a0-9(x8). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input dq0-7(x8), dq0-3(x4) input / output dqs vdd, vss power supply power supply for the memory array and peripheral circuitry. vddq, vssq power supply vddq and vssq are supplied to the output buffers only. bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre, read, write commands. data input/output: data bus data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. used to capture write data. symbol type description /qfc output fet control: optional. output during every read and write access. can be used to control isolation switches on modules. open drain output. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. input / output vref input sstl_2 reference voltage.
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 5 basic functions the m2s56d20/30tp provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table. /cs chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command clk define basic commands activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto- precharge, reada ) write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto- precharge, writea ). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read /write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. /clk
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 6 command truth table h=high level, l=low level, v=valid, x=don't care, n=clk cycle number command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a10 /ap a0-9, 11-12 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row address entry & bank activate act h x l l h h v v v single bank precharge pre h x l l h l v l x precharge all banks prea h x l l h l h x column address entry & write write h x l h l l v l v column address entry & write with auto-precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto-precharge reada h x l h l h v h v auto-refresh refa h h l l l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h x x x x x x l h l h h h x x x burst terminate term h x l h h l x x x mode register set mrs h x l l l l l l v x note 1 note: 1. applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 2. ba0-ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0-ba1 are reserved; a0-a11 provide the op- code to be written to the selected mode register. 2
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 7 function truth table current state /cs /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop l l l h x refa auto-refresh l l l l op-code, mode-add mrs mode register set row active h x x x x desel nop l h h h x nop nop l h h l ba term nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge / precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read (auto- precharge disabled) h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin new read, determine auto-precharge l h l l ba, ca, a10 write writea l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 2 2 2 4 5 5 3 2 illegal
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 8 function truth table (continued) current state /cs /ras /cas /we address command action write (auto- precharge disabled) h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto- precharge l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto- precharge l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge/illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with auto precharge h x x x x desel nop (continue burst to end) l h h h x nop nop (continue burst to end) l h h l ba term illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal l l h l ba, a10 pre / prea precharge/illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 3 3 2 2 2 2 2
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 9 function truth table (continued) current state /cs /ras /cas /we address command action pre - charging h x x x x desel nop (idle after trp) l h h h x nop nop (idle after trp) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea nop (idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row activating h x x x x desel nop (row active after trcd) l h h h x nop nop (row active after trcd) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- covering h x x x x desel nop l h h h x nop nop l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal notes 2 2 2 4 2 2 2 2 2 2 2 2
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 10 function truth table (continued) current state /cs /ras /cas /we address command action re- freshing h x x x x desel nop (idle after trc) l h h h x nop nop (idle after trc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode register setting h x x x x desel nop (idle after trsc) l h h h x nop nop (idle after trsc) l h h l ba term illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h=high level, l=low level, x=don't care ba=bank address, ra=row address, ca=column address, nop=no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and/or data-integrity are not guaranteed. notes
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 11 current state cke n-1 cke n /cs /ras /cas /we add action self- refresh h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop (maintain self-refresh) power down h x x x x x x invalid l h x x x x x exit power down to idle l l x x x x x nop (maintain self-refresh) all banks idle h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state =power down any state other than listed above h h x x x x x refer to function truth table h l x x x x x begin clk suspend at next cycle l h x x x x x exit clk suspend at next cycle l l x x x x x maintain clk suspend function truth table for cke abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command. notes 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 12 simplified state diagram row active idle pre charge power down read reada write writea power on act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada read pre reada reada pre pre prea power applied mode register set self refresh auto refresh active power down automatic sequence command sequence write read pre charge all mrs burst stop term
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 13 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or multifunctioning. 1. apply vdd before or the same time as vddq 2. apply vddq before or at the same time as vtt & vref 3. maintain stable condition for 200us after stable power and clk, apply nop or dsel 4. issue precharge command for all banks of the device 5. issue emrs 6. issue mrs 7. issue 2 or more auto refresh commands 8. maintain stable condition for 200 cycle after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when both banks are in idle state. after trsc from a mrs command, the ddr sdram is ready for new command. r: reserved for future use bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 r 2 4 8 r r r r r 2 4 8 r r r r 0 1 burst type sequential interleaved a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 dr 0 ltmode bt bl 0 0 0 /cs /ras /cas /we a11-a0 /clk v clk ba0 ba1 cl latency mode /cas latency r r 2 r r 1.5 2.5 r 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 dll reset no yes
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 14 extended mode register dll disable / enable mode can be programmed by setting the extended mode register (emrs). the extended mode register stores these data until the next emrs command, which may be issued when all banks are in idle state. after trsc from a emrs command, the ddr sdram is ready for new command. /cs /ras /cas /we a11-a0 /clk v clk ba0 ba1 0 1 dll disable dll enable dll disable a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 0 0 dd 1 0 0 ds qfc 0 0 0 0 0 1 drive strength normal weak 0 1 qfc disable enable
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 15 /cas latency burst length cl= 2 bl= 4 burst length a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 command address dq y y read write dqs q0 q1 q2 q3 d0 d1 d2 d3 /clk clk
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 16 absolute maximum ratings dc operating conditions (ta=0 ~ 70?, unless otherwise noted) capacitance (ta=0 ~ 70?, vdd = vddq = 2.5 ?0.2v, vss = vssq = 0v, unless otherwise noted) symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5 ~ 3.7 v vddq supply voltage for output with respect to vssq -0.5 ~ 3.7 v vi input voltage with respect to vss -0.5 ~ vdd+0.5 v vo output voltage with respect to vssq -0.5 ~ vddq+0.5 v io output current 50 ma pd power dissipation ta = 25 ? 1000 mw topr operating temperature 0 ~ 70 ? tstg storage temperature -65 ~ 150 ? symbol parameter limits unit min. typ. max. vdd supply voltage 2.3 2.5 2.7 v vddq supply voltage for output 2.3 2.5 2.7 v vih(dc) high-level input voltage vref + 0.18 vddq+0.3 v vil(dc) low-level input voltage -0.3 vref - 0.18 v 11 pf 3.5 2.5 co(qf) output capacitance, /qfc 11 pf 5.5 4.0 11 pf 3.5 2.5 11 pf 3.5 2.5 11 pf 3.5 2.5 i/o capacitance, i/o, dqs, dm pin ci/o input capacitance, clk pin ci(k) input capacitance, control pin ci(c) input capacitance, address pin ci(a) vi=1.25v f=100mhz vi=25mvrms notes unit max. min. limits test condition parameter symbol vref input reference voltage 1.15 1.35 v 1.25 vin(dc) input voltage level, clk and /clk -0.3 vddq + 0.3 v vid(dc) input differential voltage, clk and /clk 0.36 vddq + 0.6 v vtt i/o termination voltage vref - 0.04 v vref + 0.04 notes 6 5 7
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 17 average supply current from vdd (ta=0 ~ 70?, vdd = vddq = 2.5 ?0.2v, vss = vssq = 0v, output open, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70?, vdd = vddq = 2.5 ?0.2v, vss = vssq = 0v, unless otherwise noted) ma 9 2 160 120 140 50 15 12 12 90 2 150 ma ma 30 110 -75 self refresh current: cke 0.2v auto refresh current: t rc = t rfc (min) operating current: burst = 2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle operating current: burst = 2; reads; continuous burst;one bank active; address and control inputs changing once per clock cycle; cl = 2.5; t ck = t ck min; i out = 0 ma active standby current: /cs > v ih (min); cke > v ih (min); one bank; active-precharge; t rc = t ras max; t ck = t ck min; dq,dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle active power-down standby current: one bank active; power-down mode; cke v il (max); t ck = t ck min idle standby current: /cs > v ih (min); all banks idle; cke > v ih (min); t ck = t ck min; address and other control inputs changing once per clock cycle idd2p precharge power-down standby current: all banks idle; power-down mode; cke v il (max); t ck = t ck min ma operating current: one bank; active-read-precharge; burst = 2; t rc = t rc min; cl = 2.5; t ck = t ck min; i out = 0 ma;address and control inputs changing once per clock cycle operating current: one bank; active-precharge; t rc = t rc min; t ck = t ck min; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle parameter/test conditions 120 50 idd4r idd3n ma ma ma ma ma ma 100 15 30 100 80 idd6 idd5 idd4w idd3p idd2n idd1 idd0 notes unit -10 limits(max) symbol symbol parameter/test conditions limits min. max. unit vih(ac) vil(ac) vid(ac) vix(ac) high-level input voltage (ac) low-level input voltage (ac) input differential voltage, clk and /clk input crossing point voltage, clk and /clk vref + 0.35 vref - 0.35 v v v v 0.7 0.5*v dd q-0.2 v dd q + 0.6 ioz i i off-state output current /q floating vo=0~v dd q input current / vin=0 ~ vddq ? ? -5 -5 5 5 0.5*v dd q+0.2 notes 7 8
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 18 ac timing requirements (ta=0 ~ 70?, vdd = vddq = 2.5 ?0.2v, vss = vssq = 0v, unless otherwise noted) ns 15 12 15 12 cl=1.5 cl=2 clk cycle time tck cl=2.5 ns 15 10 15 10 16 15 14 14 ac characteristics -10 -75 2 1.25 2 1.25 4 4 1.1 0.9 1.1 0.9 0.6 0.4 0.6 0.4 1.1 0.9 1.1 0.9 0.6 0.4 0.6 0.4 1.2 1.1 1.2 1.1 0.25 0.25 0.6 0.4 0.6 0.4 0 0 15 15 0.2 0.2 0.2 0.2 0.35 0.35 0.35 0.35 1.25 0.75 1.25 0.75 0.35 0.35 +0.6 -0.6 +0.5 -0.5 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 2 1.75 ns ns tck tck tck tck ns ns tck tck ns ns tck tck tck tck tck tck ns ns ns ns ns ns ns 0.6 0.5 0.6 0.5 15 8 15 7.5 tck 0.55 0.45 0.55 0.45 tck 0.45 0.55 0.45 +0.8 -0.8 +0.75 -0.75 +0.8 -0.8 +0.75 -0.75 max. min. max. min. parameter 0.55 tqoh tqck /qfc output hold time for writes /qfc output access time from clk//clk, for write /qfc postamble during reads tqpst /qfc preamble during reads tqpre read preamble trpre read postamble trpst twpre write preamble twpst write postamble twpres write preamble setup time input hold time (address and control) tih tis input setup time (address and control) tmrd mode register set command cycle time tdsh dqs falling edge hold time from clk tdss dqs falling edge to clk setup time tdqsl dqs input low level width tdqsh dqs input high level width tdqss write command to first dqs latching transition tdv dq and dqs data valid window tdqsq dq valid data delay time from dqs data-out-low impedance time from clk//clk tlz thz data-out-high impedance time from clk//clk tdipw dq and dm input pulse width (for each input) input hold time(dq,dm) input setup time (dq,dm) tds tdh tcl clk low level width tch clk high level width ns dq output valid data delay time from clk//clk tdqsck dq output valid data delay time from clk//clk ns tac notes unit symbol
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 19 18 17 7.8 7.8 1 1 1 1 200 200 80 75 1 1 15 15 15 15 20 20 20 20 80 75 70 65 120,000 50 120,000 45 us tck tck tck ns tck ns ns ns ns ns average periodic refresh interval trefi exit power down to -read command txprd exit power down to command txpnr txsrd exit self ref. to -read command txsnr exit self ref. to non-read command twtr internal write to read command delay ns 35 35 auto precharge write recovery + precharge time tdal -10 -75 ac characteristics max. min. max. min. parameter twr write recovery time trrd act to act delay time row precharge time row to column delay trp trcd trfc auto ref. to active/auto ref. command period ns row cycle time(operation) trc row active time ns tras notes unit symbol output load condition dq output timing measurement reference point v ref v ref dqs v out v ref 30pf 50 w v tt =v ref zo=50 w v tt =v ref 50 w 25 w 10cm ac timing requirements(continues) (ta=0 ~ 70?, vdd = vddq = 2.5 ?0.2v, vss = vssq = 0v, unless otherwise noted)
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 20 notes 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed +/-2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specifications are tested after the device is properly initialized. 11. this parameter is sampled. vddq = +2.5v ?.2v, vdd = +2.5v ?.2v , f = 100 mhz, ta = 25?, vout(dc) = vddq/2, vout(peak to peak) = 25mv. dm inputs are grouped with i/o pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke =< 0.3vddq is recognized as low. 14. t hz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specific requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode.
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 21 /clk dqs tis tih vref clk valid data /qfc read operation tac tdqsck tcl tch tck tdqsq tdv trpre trpst dqs /qfc /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=max. tdss twpres twpst tqck tqoh(min) tqpre tqpst dqs /qfc /clk clk tdqss tds tdh tdqsl tdqsh twpre write operation / tdqss=min. tdsh twpres twpst tqck tqoh(max) dq dq dq cmd & add.
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 22 a precharge command can be issued at bl/2 from a read command without data loss. precharge all bank activation and precharge all (bl=8, cl=2) command a0-9,11-12 a10 ba0,1 dq act xa xa 00 read y 0 00 act xb xb 01 pre trrd trcd 1 act xb xb 01 tras trp trcmin 2 act command / trcmin dqs qa0 bl/2 operational description bank activate the ddr sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row address a11-0. the minimum activation interval between one bank and the other bank is trrd. maximum 2 act commands are allowed within trc,although the number of banks which are active concurrently is not limited. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea,pre+a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. qa1 qa2 qa3 qa4 qa5 qa6 qa7 /clk clk
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 23 multi bank interleaving read (bl=8, cl=2) /clk command a0-9,11-12 a10 ba0,1 dq act xa xa 00 read y 0 00 read y 0 10 act xb xb 10 pre 0 00 trcd /cas latency burst length dqs qa0 read after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl-1) consecutive data when the burst length is bl. the start address is specified by a11,a9-a0(x4)/a9-a0(x8), and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge(reada) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl/2 after reada. the next act command can be issued after (bl/2+trp) from the previous reada. clk qa1 qa2 qa3 qa4 qa5 qa6 qa7 qb0 qb1 qb2 qb3 qb4 qb5 qb7 qb8
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 24 read with auto-precharge (bl=8, cl=2) command a0-9,11-12 a10 ba0,1 dq act xa xa 00 read y 1 00 act xb xb 00 internal precharge start trcd trp bl/2 + trp bl/2 dqs /clk clk read auto-precharge timing (bl=8) command act read internal precharge start timing dq dq cl=2.5 cl=1.5 bl/2 qa0 dq cl=2 qa0 /clk clk qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa1 qa2 qa3 qa4 qa5 qa6 qa7 qa1 qa2 qa3 qa4 qa5 qa6 qa7
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 25 write after trcd from the bank activation, a write command can be issued. 1st input data is set from the write command with data strobe input, following (bl-1) data are written into ram, when the burst length is bl. the start address is specified by a11,a9-a0(x4)/a9-a0(x8), and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last data to the pre command, the write recovery time (twrp) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any command(read,write,pre,act) to the same bank is inhibited till the internal precharge is complete. the next act command can be issued after tdal from the last input data cycle. multi bank interleaving write (bl=8) command a0-9,11-12 a10 ba0,1 dq act xa 00 write 00 write 0 0 10 act xb 10 0 10 trcd trcd pre xa 0 00 pre dqs write with auto-precharge (bl=8) command a0-9,11-12 a10 ba0,1 dq act xa 00 write 1 00 act xb 00 trcd da0 dqs /clk clk /clk clk da1 da2 da3 da4 da5 da6 da7 da0 da1 da2 da3 da4 da5 da6 da7 db0 db1 db2 db3 tdal db4 db5 db6 db7 xa y xb xa ya yb xb
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 26 burst interruption [read interrupted by read] burst read operation can be interrupted by new read of any bank. random column access is allowed. read to read interval is minimum 1clk. [read interrupted by precharge] burst read operation can be interrupted by precharge of the same bank. read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by precharge (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 read interrupted by read (bl=8, cl=2) command a0-9,11 a10 ba0,1 dq yi read read read read yj yk yl 0 0 0 0 00 10 00 01 dqs qai0 qai1 qaj0 qaj1 qaj2 qaj3 qak0 qak1 qak2 qak3 qak4 qak5 qal0 qal1 qal2 qal3 qal4 qal5 qal6 qal7 /clk clk /clk clk dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 27 read interrupted by precharge (bl=8) cl=2.0 /clk clk command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 pre read read pre read pre dqs dqs cl=1.5
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 28 [read interrupted by burst stop] burst read operation can be interrupted by a burst stop command(term). read to term interval is minimum 1 clk. a term command to output disable latency is equivalent to the /cas latency. as a result, read to term interval determines valid data length to be output. the figure below shows examples of bl=8. read interrupted by term (bl=8) cl=2.5 command dqs command dq command dq q0 q1 q2 q3 q0 q1 /clk clk dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs cl=2.0 command dqs command dq command dq q0 q1 q2 q3 q0 q1 dq q0 q1 q2 q3 q4 q5 term read read term read term dqs dqs
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 29 [read interrupted by write with term] read interrupted by term (bl=8) cl=2.5 command dq q0 q1 q2 q3 /clk clk read term dqs write d0 d1 d2 d3 d4 d5 cl=2.0 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 d6 d7 cl=1.5 command dq q0 q1 q2 q3 read term dqs write d0 d1 d2 d3 d4 d5 d6 d7
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 30 write interrupted by write (bl=8) command a0-9,11 a10 ba0,1 write yi 0 00 write yk 0 10 write yj 0 00 write yl 0 00 [write interrupted by write] burst write operation can be interrupted by write of any bank. random column access is allowed. write to write interval is minimum 1 clk. [write interrupted by read] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. internal write to read command interval(twtr) is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". twtr is referenced from the first positive edge after the last data input. dq dai1 daj1 daj3 dak1 dak3 dak5 dal1 dqs dal2 dal3 dal5 dal6 dal7 dal4 dal0 dak4 dak2 dak0 dai0 daj0 daj2 /clk clk write interrupted by read (bl=8, cl=2.5) command a0-9,11-12 a10 ba0,1 dq write yi 0 00 read yj 0 00 dai0 dai1 qaj0 qaj1 qaj2 qaj3 qs qaj4 qaj5 qaj6 qaj7 dm twtr /clk clk
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 31 [write interrupted by precharge] write interrupted by precharge (bl=8, cl=2.5) command a0-9,11-12 a10 ba0,1 dq write yi 0 00 pre 00 dai0 dai1 qs burst write operation can be interrupted by precharge of the same or all bank. random column access is allowed. twr is referenced from the first positive clk edge after the last data input. dm twr /clk clk
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 32 [initialize and mode register sets] command /clk clk emrs pre nop mrs pre ar ar mrs act code code xa code xa 1 0 xa a0-9,11,12 a10 code 1 ba0,1 dqs dq 1 0 0 0 0 code tmrd tmrd trp trfc trfc tmrd [auto refresh] single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l,/we=cke=h) command. the refresh address is generated internally. 8192 refa cycles within 64ms refresh 256mbits memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trfc . any command must not be supplied to the device before trfc from the refa command. auto-refresh /ras cke /cs /cas /we a0-12 ba0,1 nop or deselect trfc auto refresh on all banks auto refresh on all banks /clk clk
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 33 [self refresh] self -refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l,/we=h,cke=l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. self-refresh /ras cke /cs /cas /we a0-12 ba0,1 txsnr self refresh exit /clk clk x y x y txsrd
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 34 [asynchronous self refresh] asynchronous self -refresh mode is entered by cke=l within 2 tclk after issuing a refa command (/cs=/ras=/cas=l,/we=h). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enable input, all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke for longer than txsnr/txsrd. asynchronous self-refresh /ras cke /cs /cas /we a0-12 ba0,1 txsnr self refresh exit max 2 tclk /clk clk
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 35 [power down] the purpose of clk suspend is power down. cke is synchronous input except during the self-refresh mode. a command at cycle is ignored. from cke=h to normal function, dll recovery time is not required in the condition of the stable clk operation during the power down mode. /clk clk power down by cke command pre cke command act cke standby power down active power down nop nop dm function(bl=8,cl=2) command dqs dq dm write read d0 d1 [dm control] dm is defined as the data mask for writes. during writes,dm masks input data word by word. dm to write mask latency is 0. d3 d4 d5 d6 d7 masked by dm=h don't care q2 q3 q4 q5 /clk clk q0 q1 q6 valid nop nop valid txpnr/ txprd
sep.'99 preliminary mitsubishi lsis mitsubishi electric ddr sdram (rev.0.0) m2s56d20/ 30 tp 256m double data rate synchronous dram 36 keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. all information contained in these materials,including product data, diagrams and charts,represent information on products at the time of publication of these materials,and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular,medical,aerospace,nuclear,or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject the japanese export control restrictions,they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.

▲Up To Search▲

Price & Availability of M2S56D20TP-75

	To Download M2S56D20TP-75 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .